This invention relates to integrated circuits (IC""s), and more particularly to pin-to-pin electro-static-discharge (ESD) protection structures.
Relatively small electric shocks that might not be noticed by a human can melt or otherwise destroy tiny structures in an integrated circuit (IC). To reduce such damage, input and output pads of IC chips are typically connected to protection devices specifically designed to shunt electro-static-discharges (ESD). These ESD-protection devices are effective when the ESD pulse is applied to an input or output (I/O) pin when the ground pin is connected to a ground.
During testing for ESD-protection, an ESD test machine applies a positive or negative test to the device-under-test (DUT) with its pins configured in various combinations (see JESD22-A114-B for details). This can include a zap to an I/O pin while the ground pin is connected to the ESD machine as a ground.
Since an actual electric shock can occur between any two pins on a chip, full ESD testing usually includes applying an ESD pulse between every possible combination of two pins. Other pins of the chip can be left floating.
ESD-protection devices are usually designed to shunt ESD current from a pin to a power or ground bus. When the ground is floating the ESD-protection device may not work optimally. For example, when an ESD pulse is applied between two different I/O pins, and the power and ground pins are left floating, the ESD current must somehow travel from the one I/O pin to the other I/O pin. Often an indirect path carries the ESD pulse, such as an internal ground bus.
Such I/O-pin to I/O-pin ESD testing can be the most difficult test to pass, especially for Bus-Switch-type products. While xe2x80x9cnormalxe2x80x9d I/O pin to ground or I/O-pin to power tests may pass, ESD pulses between two I/O pins with the ground pin floating may cause damage. This damage can sometimes result in leakage on a pin after the ESD test.
FIG. 1 is a diagram of a prior-art chip with grounded ESD-protection devices on each I/O pin. Pin A and pin B are I/O pins on an IC chip. Pins A and B are connected by bus-switch transistor 10 which forms a connecting channel when its gate is driven high by inverter 18. When enable EN is high, inverters 16, 18 drive the gate of bus-switch transistor 10 high, connecting pins A, B. When EN is low, transistor 10 isolates pin A from pin B.
ESD protection device 12 is connected to pin A. A wide variety of ESD protection devices could be used. ESD protection device 12 includes structures to shunt an ESD pulse from pin A to an internal ground bus. The shunt could be provided by a large diode to ground, or by a large grounded-gate n-channel transistor (either thin gate oxide or field oxide gate could be used), or by some other structure.
When an ESD pulse is applied to pin A, and the ground pin is grounded, ESD protection device 12 shunts the ESD pulse to the internal ground, and then to the ground pin and back to the ESD tester (or other common ground). ESD protection device 12 protects bus-switch transistor 10 from damage by the ESD pulse.
Pin B is likewise protected by ESD protection device 14. During normal operation in a real system, when EN is low and bus-switch transistor 10 isolated pins A, B, ESD protection device 12 can shunt any shock applied to pin A to the internal ground. This prevents the shock from being coupled to pin B, which may be coupled to another active bus. Such shocks can occur during hot-swapping of PC or network cards.
ESD-Protection Can Fail When internal Ground Floatsxe2x80x94FIG. 2
While ESD protection devices 12, 14 provide good protection when the internal ground is connected to an external ground, protection can be poor when the internal ground is floating. FIG. 2 highlights failure of ESD-protection devices when the internal ground is floating. In this I/O-pin to I/O pin ESD test the power and ground pins are left floating. The ESD machine is connected between pin A and pin B. The ESD pulse is applied to pin A while pin B is grounded. All other pins, including power and ground, are left floating.
The ESD pulse applied to pin A charges up any capacitances on pin A until a high enough voltage is reached so the ESD protection device 12snaps back and conducts. Then the ESD pulse charges internal ground bus 20. Internal ground bus 20 connects to other ESD protection devices including ESD protection device 14 for the grounded pin B. The ESD pulse then travels in the forward direction through ESD protection device 14 to reach pin B.
Internal ground bus 20 has some resistance, as does ESD protection device 14 and especially ESD protection device 12, which has to snapback before conduction occurs. The total potential drop in this discharge path can be equal to the sum of the Snapback voltage of protection device 12 plus the IR drop across internal ground bus 20 plus the forward voltage of protection device 14.
The n+ drain, p-substrate, and n+ source of bus-switch transistor 10 form parasitic lateral NPN transistor 22. The drain of bus-switch transistor 10 at pin A receiving the ESD zap is the collector, the source at pin B, which is grounded is the emitter, and the p-substrate is the base of NPN transistor 22. Since internal ground bus 20 is floating during the pin-to-pin ESD test, the p-substrate, which is normally grounded, is also floating. Thus NPN transistor 22 has a floating or open base.
The floating base lowers the breakdown voltage of NPN transistor. The open-base breakdown voltage is known as BVCEO to indicate the open (O) base condition. This open-base breakdown can be lower than the snapback or turn-on voltage of ESD protection device 12.
Thus NPN transistor 22 can conduct before ESD protection device 12 conducts during a pin-to-pin ESD test. Since NPN transistor 22 is simply a parasitic device and is not designed to carry the high ESD current, various material failures can occur, permanently damaging the IC.
To prevent such damage, NPN transistor 22 and bus-switch transistor 10 can have a more rugged design. For example, the source and drain contacts can be moved farther from the gate edge, or a larger channel length can be used, effectively increasing the base-width of parasitic NPN transistor 22. However, these design changes can increase the capacitance and ON resistance, which is undesirable. Even with these design changes, bus-switch transistor 10 may still fail the I/O-pin to I/O-pin ESD test.
A related application for xe2x80x9cESD-isolation Circuit Driving Gate of Bus-Switch Transistor During ESD Pulse Between Two I/O Pinsxe2x80x9d, filed Mar. 7, 2002, U.S. Ser. No. 09/683,968 describes improving ESD immunity of a bus-switch transistor by actively driving the transistor gate during an ESD event. While useful, additional ESD is desired. The present invention can be used in conjunction with the related application or separately.
What is desired is improved ESD protection. Better ESD protection is desired for I/O-pin to I/O-pin ESD tests when ground and the substrate is floating. An isolation circuit for a bus-switch transistor is desired that is activated during I/O-pin to I/O-ESD tests or similar conditions.